Noisecom Noise on Vcc for Serial Data Communications

by Vitali Penso  
Wireless Telecom Group

Abstract

The supply voltage (Vcc) specification is a key parameter for almost all integrated circuits’ (IC) datasheets. Unless its requirements are met there is no way to know if the remaining IC specifications will be valid. Therefore before specifying the operational supply voltage range of a device, designers, verification and quality engineers use the results of extensive testing to make sure the IC meets all the specification requirements within the tested Vcc voltage range.

Figure 1 JV9000 block diagram.

The supply voltage (Vcc) specification is a key parameter for almost all integrated circuits’ (IC) datasheets. Unless its requirements are met there is no way to know if the remaining IC specifications will be valid. Therefore before specifying the operational supply voltage range of a device, designers, verification and quality engineers use the results of extensive testing to make sure the IC meets all the specification requirements within the tested Vcc voltage range. With the exception of the power supply rejection ratio (PSRR) specification of some analog and RF ICs, what is often not specified or ignored is the immunity of the IC to noise and spurs riding on its supply voltage.

IC design verification testing is typically done using clean lab power supplies and well shielded power supply cables to baseline performance under ideal conditions. Yet those conditions are almost never the operating conditions and environment of the IC in real life circuits and applications. As a result, almost all IC manufacturers provide reference designs and board layout practices to minimize noise on Vcc. In the end, the responsibility of providing clean Vcc to the IC is placed on the board designer whose specific application and operating environment may require taking additional precautions beyond datasheet reference design and application circuit recommendations. Unless specific information is provided by the IC manufacturer about the noise immunity of the device, the board designer may be forced to overdesign the support circuitry which, given space and cost constraints, is not always possible. The designer may have to make educated guesses or be forced to plan for an additional board spin to verify there are no immunity issues. The additional work inevitably can delay product release and increase development cost.

Although the concept of noise on Vcc is nothing new, advancements in IC die technology over the past decade have introduced new challenges. Mainly through die shrinking, higher levels of integration and lower supply voltages have been achieved resulting in reliability, cost and performance benefits such as reduced parts count, improved power efficiency and thermal performance. In the meantime, the IC board level designer has new design challenges introduced by the lower supply and I/O voltage. What was once an insignificant amount of noise on the Vcc of a 3.3 or 5 V circuit can no longer be ignored on a 1.2 V IC due to lower noise margins. Furthermore, the integration of digital, analog and RF functionalities on a single IC operating at ever higher data rates can generate higher internal noise, making the low voltage and high speed device more susceptible to added external noise and ripple on Vcc.


Figure 2 The test set-up diagram.

Noise on Vcc impacts a wide range of applications and circuits. In transceivers, receiver sensitivity and transmitter spurious emission performance may degrade due to noise on the Vcc of an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). Similarly, for clocking and local oscillator (LO) circuits with PLL/VCOs and PLL/VCXO/XOs used in transceiver designs, noise on Vcc can generate clock jitter and LO phase noise impacting spurious emissions and receiver sensitivity. In high speed serial data communication circuits the clock jitter caused by noise and spurs on the Vcc of the PLL/XO circuitry can cause data jitter potentially degrading BER performance.

Figure 3 "Clean" error free channel BER = 0 (J7000 & JV9000 both off, not injecting noise).

In this application note, we look at a high speed data/clock buffer IC, DUT, and the effect noise on its Vcc has on overall system performance. In characterizing system performance, BER testing is used to measure the system performance and is supplemented by eye diagrams as a visual tool. The injection of additive white Gaussian noise (AWGN) and CW tones into the Vcc path of the DUT is accomplished using Noisecom’s JV9000 unit. The unit intakes a clean power supply voltage and injects CW tones and/or AWGN signal in a controlled manner with 0.1 dB precision (see Figure 1).

We also use the jitter generator to degrade the BER performance of the channel. The unit injects AWGN noise on serial data which in turn causes random jitter, Rj. The jitter is created during the transitions from a 0 to a 1 or from a 1 to a 0 when the noise added to the signal during this transitional period causes the receiver to interpret the timing of the transition incorrectly. The resulting timing uncertainty is called jitter, and in case of AWGN it is random. The unit’s high crest factor output allows the generation of realistic peaks that makes it ideal for BERT testing and can be used as a random jitter source for various serial data bus applications, including PCI Express Gen I & II, Serial ATA, Fiber Channel, 10, 40, and 100 GB Ethernet (802.3).

In the test set up, BERT’s pattern generator is used as a high speed differential serial data source and the BERT output is connected to the J7000. Note that the J7000 is operating in bypass mode (no noise added) for the initial part of the test. It is turned on for the second phase of our test to degrade the serial link performance by introducing random jitter. The output of the J7000 feeds the DUT, the output of the DUT then drives the BERT detector input, looping the signal back into the BERT receiver. The Vcc of the DUT comes from the JV9000, also initially configured with all its noise and spur signals turned off, providing a clean supply voltage to the eval board for baseline testing. A block diagram of the set up is shown in Figure 2.

	Figure 4 BER vs. CW (spur) frequency.

In order to mimic how an IC designer or verification engineer would test for immunity of the IC to noise and spurs on its Vcc, bypass capacitors of the DUT eval board were removed; enabling the tester to see which frequencies riding on the Vcc have the greatest impact on system performance. Before presenting the test procedure and results it is important to note that for actual IC performance verification testing, the designer or test engineer would likely use a special fixture, free of parasitic effects of an evaluation board, in order to measure the raw performance of the IC. In this test set up, it is very likely that parasitic effects of the eval board play a role in the outcome. In fact the test set up may be closer to how a circuit board designer would test the noise immunity of a circuit given a particular board layout and its parasitics.

Figure 5 BER = 1 E-07 (J7000 injecting AWGN noise –10 dBm, JV9000 off).

Test Procedure

1. Both JV9000 and J7000 noise and spur sources are turned off to establish baseline performance with BER = 0 (see Figure 3).
2. JV9000 AWGN path is turned on and the injected noise level is increased slowly as the BER is monitored.
3. JV9000 AWGN noise source is turned off and CW tones of 10 kHz, 100 kHz, 1 MHz, 10 MHz and 100 MHz are injected one at a time to see how the BER changes at each frequency. Note that CW coupling from the Vcc to the data outputs will cause deterministic jitter, Dj.
4. And finally, step 3 is repeated with the AWGN noise turned on to see the combined effect AWGN and CW spurs have on BER performance.
5. We then turn off all broadband noise and CW signals on the JV9000 and degrade the channel BER to 1E-07 by injecting AWGN on to the data lines using the J7000 jitter generator and creating random jitter, Rj. The same tests that are performed at steps 2, 3 and 4 are repeated on the 1 E-7 BER channel to see the combined impact of AWGN noise and spurs on Vcc have on the already degraded channel.

The results of the tests can be summarized by noting that when the initial channel BER is 0 and the AWGN noise and CW tones injected onto the Vcc are at the maximum standard levels (0 dBm tones at the mentioned frequencies and 0 dBm total AWGN power from 500 Hz to 2 GHz) we could not introduce any significant bit errors even though the added noise could easily be seen on the eye diagram. So there is evidence of the existence of noise leaking from the Vcc pin to the data output pins but there is no effect on BER performance. However, when the BER is degraded to 1 E-07 by injecting AWGN noise onto the data lines, creating random jitter, the added noise and spurs do play a very significant role where the BER is now degraded from 1 E-07 up to 7 E-05 when a 1 MHz CW tone is injected. It is also worth noting that switching power supplies generally switch at anywhere from 100 kHz to a few MHz, so an IC’s Vcc noise immunity at these low frequencies is important in most designs.

The test results are presented in a tabular format in Table 1 where the channel BER is baselined at 1 E-07. For a graphical view of how the DUT responded to various injected frequencies on its Vcc see Figure 4.

Injecting broadband noise (AWGN) from 500 Hz to 2 GHz into the Vcc of the IC (DUT) increases the system BER to just over twofold. However, when the injected power is concentrated at one frequency (CW) then impact is much greater. As the frequency of the injected constant power tone into the Vcc pin of the IC changes so does the impact on the receiver. We see a BER resonance at around 1 MHz, where the BER degrades the most, when a CW tone at 1 MHz is injected.

Figure 6 BER = 9 E-05 (J7000 injecting AWGN noise, JV9000 injecting AWGN and 1 MHz CW).

Figures 3, 5 and 6 are eye diagrams for various test conditions. Figure 3 shows the eye diagram when BER=0 and all noise sources are turned off. Figure 5 shows the eye diagram BER= 1 E-07 when only J7000 is injecting noise (JV9000 noise sources are off). Figure 6 shows the eye diagram for the received signal under worst case spur and noise conditions (1 MHz CW + AWGN) when the baseline channel performance is BER is 1E-07.

Conclusion

As the Vcc levels and IC logic levels drop and the integration of multiple functions in a mixed signal environment generates more noise within the IC, the need to test for impact of noise and spurs on Vcc on the IC operation becomes increasingly important. The goal of this application note is to show how IC performance verification engineers and circuit designers can characterize the operation of an IC or circuit in the presence of noise and spurs on Vcc. The test results show that an IC can be more sensitive to noise and spurs riding on its Vcc at certain frequencies. Additionally, the combination of data jitter and Vcc noise may impact the receiver performance very differently than what one may surmise from individual independent tests. Taking it a step further, the testing performed in accordance with this application note is also necessary when an IC designer, an application engineer or a circuit designer needs to decide what filtering is required on Vcc for optimum IC performance.

There are many home-made solutions adopted to perform these tests. When multiple test stations need to be built or design teams in different geographic regions need to work together, an integrated test set up allows test and verification engineers to perform their testing in a repeatable and controlled manner. There are also the savings associated in programming, bench space, set-up and system verification, as well.