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Testing Effect of Noise & Spurs on Vcc of a PLL/VCO integrated circuit

Broadcasted 7/17/2014

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In this short video clip we show how a designer or verification engineer can easily test effects of noise and spurs riding on the Vcc of their PLL/VCO circuit. We baseline the PLL/VCO phase noise performance with no noise (AWGN) or spurs (CW tones) injected. We then introduce broadband noise to the Vcc and repeat phase noise measurements to see impact of AWGN. The measurements are repeated for 10 KHz, 100 KHz, 1 MHz and 10 MHz CW tones. The test set-up consists of a clean power supply, JV9000 noise on Vcc test solution, PLL/VCO eval board (DUT) and a phase noise analyzer (BNC model 7300). The simplicity of the testing shown in this video highlights the advantages of using an integrated solution like JV9000 where a noise generator, a CW signal generator and combiners, attenuators and bias-t are all integrated into one box allowing noise immunity testing within minutes.

Testing Effect of Noise on Vcc for serial data communications

Broadcasted 4/10/2014

SuperUser Account 0 375

This short video clip demonstrates the impact of noise and spurs on Vcc of an IC for high speed serial data communication IC. For this demonstration we generate pseudo random data clocked at 1.6 GHz using a BERT. Onto the high speed differential signal path we introduce Noisecom’s J7000 random jitter generator which takes in the differential serial data and adds AWGN noise to it. The output of J7000 then drives a data/clock buffer IC as a DUT (see diagram below). The Vcc of the IC is connected to the JV9000, our noise on Vcc test solution that introduces noise and spurs on the Vcc supply voltage an IC. The output of the IC is terminated at the detector inputs of the BERT for BER and eye diagram analysis.

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